Generally, in integrated circuit design, a circuit layout is simulated before fabrication begins to determine a yield probability. The yield probability may then, for example, be used to determine whether a sufficient amount of chips may be predicted to have proper functionality to justify the costs of chips that are non-functional due to processing variations. As is known in the art, processing variations may result in non-ideal devices that may affect the functionality of the chip.
Many integrated circuits include parallel paths, and techniques to determine the yield probability of these integrated circuits may treat the circuits as one-dimensional during simulation. These techniques may have deficiencies. For example, one method may simulate the circuits by requiring long vectors and a long simulation time. In this method, each of N parallel paths may be simulated as N serial jobs of full circuitry. Thus, this method may require more random variables and a long simulation time. In another technique, the yield probability may be calculated using complex probability calculations. This method may not provide an intuitive yield probability for the integrated circuits, and thus, this method may not be easily understood.
Accordingly, there is a need in the art to overcome these stated deficiencies.